1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly, to an operational amplifier of a drive circuit of an LCD (Liquid Crystal Display) source driver employed in a liquid crystal display.
2. Description of Related Art
An active matrix type liquid crystal display includes scan lines and data lines in a row direction and a column direction, respectively, and pixels are arranged in matrix in intersections of the scan lines with the data lines. An active element (formed by a Thin Film Transistor or the like) is arranged in each of the pixels. A gate electrode of the active element is connected to the scan line, and a drain electrode is connected to the data line. Further, one terminal of a liquid crystal capacitor as an equivalent of a capacitive load is connected to a source electrode of the active element, and the other terminal of the liquid crystal capacitor is connected to a common electrode line. A scan line drive circuit and a data line drive circuit are connected to the scan line and the data line, respectively.
In the liquid crystal display, the scan lines are scanned in series from the top to the bottom by the scan line drive circuit, so as to apply voltage from the data line drive circuit to the liquid crystal capacitor through the active element arranged in each pixel. In the liquid crystal display, the arrangement of the liquid crystal molecules is changed in accordance with the voltage applied to the liquid crystal capacitor, whereby the light transmission ratio varies.
In the known liquid crystal display, the polarity of the voltage that is applied to the liquid crystal capacitor from the data line through the active element (hereinafter referred to as pixel voltage) is inverted at every predetermined period. In summary, the pixels are driven in an alternate manner, and this is because the physical property is degraded while time passes when a certain voltage is applied to the liquid crystal capacitor. Now, the polarity indicates positive or negative of the pixel voltage on the basis of the voltage of the common electrode line of the liquid crystal (Vcom). For example, a dot inversion drive method and a two-line-dot inversion drive method are known as the method of driving the pixels. The dot inversion drive method is the method of inverting the polarity of the pixel voltage every time one scan line is scanned, and the two-line-dot inversion drive method is the method of inverting the polarity of the pixel voltage every time two scan lines are operated.
Recent trend of large liquid crystal displays has brought about increase of the resolution and the display size of the liquid crystal panel. The increase of the resolution and the display size of the liquid crystal panel has brought about increase of the number of data lines and its length to be driven and increase of the number of pixels connected to one data line. This leads to increase of the load of the panel driven by the LCD source driver. Among the characteristic parameters of the output buffer of the LCD source driver, slew rate is the important characteristic parameter to judge visible failures of the image quality. In short, the increase of the load capacitance results in degradation of the slew rate of the output of the LCD source driver. In order to prevent this, characteristic of the slew rate of the output buffer needs to be enhanced in order to drive higher load.
FIG. 8 is a circuit diagram showing the structure of an operational amplifier disclosed in Japanese Unexamined Patent Application Publication No. 61-35004. This operational amplifier is a typical amplifier including a class AB output stage that is push-pull driven. This circuit includes a differential amplifier 1, P channel MOS transistors 2, 3, N channel MOS transistors 4, 5, constant voltage sources 6, 7, and constant current sources 8, 9.
An output terminal VOUT1 and a minus input of the differential amplifier 1 are voltage-follower connected. An output AOUT1 of the differential amplifier 1 amplifies an input terminal SIN1 and is connected to a drain of the P channel MOS transistor 2, a source of the N channel MOS transistor 4, a gate of the N channel MOS transistor 5, and the constant current source 9.
The other terminal of the constant current source 9 is connected to a negative voltage power supply VSS. A source of the N channel MOS transistor 5 is connected to the negative voltage power supply VSS, and a drain is connected to the output terminal VOUT1, a drain of the P channel MOS transistor 3, and the minus input of the differential amplifier 1. The P channel MOS transistor 3 includes a source connected to a positive power supply voltage VDD, a gate connected to the constant current source 8, a source of the P channel MOS transistor 2, and a drain of the N channel MOS transistor 4, and a drain connected to the output terminal VOUT1, the drain of the N channel MOS transistor 5, and the minus input of the differential amplifier 1.
The other terminal of the constant current source 8 is connected to the positive voltage power supply VDD. A gate of the P channel MOS transistor 2 is connected to the positive voltage power supply VDD through the constant voltage source 6, and is biased to be lower than the positive voltage power supply VDD by a certain voltage. A gate of the N channel MOS transistor 4 is connected to the negative voltage power supply VSS through the constant voltage source 7, and is biased to be higher than the negative voltage power supply VSS by a certain voltage.
Next, the operation of the circuit shown in FIG. 8 will be described. In FIG. 8, the output terminal VOUT1 in the output stage responds to the input SIN1 of the differential amplifier 1. The P channel MOS transistor 3 and the N channel MOS transistor 5 that are connected in series both flow the same zero input current (I1=I2).
The constant current source 8 flows I3 from the positive voltage power supply VDD to a node to which the gate of the P channel MOS transistor 3 is connected. I3 is separated into two parts I4 and I5, and each of them flows to the P channel MOS transistor 2 and the N channel MOS transistor 4, respectively. The P channel MOS transistor 2 and the N channel MOS transistor 4 are complementary transistors connected between the gate of the P channel MOS transistor 3 and the gate of the N channel MOS transistor 5.
The constant current source 9 flows I6 to the negative voltage power supply VSS from a node to which the gate of the N channel MOS transistor 5 is connected. The differential amplifier 1 demodulates current I7 that flows in the constant current source 9 as a part of I6 (I6=I4+I5+I7).
The bias structure that includes the constant current sources 8, 9 operates the P channel MOS transistor 2 and the N channel MOS transistor 4 as common gate unity gain level shifters.
Upon modulating I7 by the differential amplifier 1, the gate potential of the N channel MOS transistor 5 varies, which varies I2. In short, as I7 increases, the gate potential of the N channel MOS transistor 5 increases. Now, as I6 is constant, I5 decreases. This raises the potential of the gate of the P channel MOS transistor 3, which causes reduced I1, and the output terminal VOUT1 attenuates the current as a result. Since the drain of the N channel MOS transistor 4 is connected to the source of the P channel MOS transistor 2, the common gate connection generates unity gain from the gate of the N channel MOS transistor 5 to the gate of the P channel MOS transistor 3.
Meanwhile, I5 increases as the differential amplifier 1 decreases I7. Thus, the gate potential of the N channel MOS transistor 5 is decreased, which decreases I2. The operation of the N channel MOS transistor 4 decreases the gate potential of the P channel MOS transistor 3, which increases I1, and thus the output terminal VOUT1 supplies current as a result. As stated above, the P channel MOS transistor 3 and the N channel MOS transistor 5 are push-pull driven.
Next, one example of the differential amplifier is shown in FIG. 9. This differential amplifier includes P channel MOS transistors 10, 11 that form a differential pair, N channel MOS transistors 12, 13 that form a current mirror circuit, and a P channel MOS transistor 14 that functions as a constant current source. Gates of the P channel MOS transistors 10, 11 are connected to an inverting input terminal Vin(−), and a non-inverting input terminal Vin(+), respectively. The inverting input terminal Vin(−) is a minus input of the differential amplifier 1 shown in FIG. 8, and is voltage-follower connected to the output terminal VOUT1. The P channel MOS transistor 14 that functions as the constant current source has a source connected to the positive voltage power supply VDD, a drain connected to sources of the P channel MOS transistors 10, 11, and a gate connected to a bias power supply BP1 to flow constant drain current I8.
The N channel MOS transistor 12 has a source connected to the negative voltage power supply VSS, and a gate and a drain connected to a drain of the P channel MOS transistor 10. The N channel MOS transistor 13 has a source connected to the negative voltage power supply VSS, a gate connected to the gate of the N channel MOS transistor 12, and a drain connected to a drain of the P channel MOS transistor 11. A node in which the drain of the P channel MOS transistor 11 and the N channel MOS transistor 13 are connected is the output terminal AOUT1 of the differential amplifier. The output terminal AOUT1 is the output of the differential amplifier 1, and is connected to the gate of the N channel MOS transistor 5 of the amplifier shown in FIG. 8.
Next, the operation of the differential amplifier shown in FIG. 9 will be described. In the differential amplifier shown in FIG. 9, the differential input signal applied to the inverting input terminal Vin(−) and the non-inverting input terminal Vin(+) is received in the P channel MOS transistors 10, 11 that form a differential pair. An output of the differential pair appears in the drains of the P channel MOS transistors 10, 11. This differential signal is input to the N channel MOS transistors 12, 13 of the current mirror circuit that functions as an active load. The N channel MOS transistors 12, 13 convert the differential output signal to a single end signal. The signal that is converted to the single end signal is the output signal of the amplifier, and is output from the output terminal AOUT1.